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Functional Block Descriptions
1
Functional Description
CorePCIF consists of three major functional blocks, shown in Figure 1-1 . These blocks are the Target Controller,
Master Controller, and Datapath. With both a Target and Master, all three blocks are required. Otherwise, only the
Datapath and either the Target or Master function are required.
CorePCIF
Master Controller
DMA
Registers
Target Controller
PCI Bus
PCI
Configuration
Address
Decoder and
Select Logic
Datapath
Datapath
Controller
PCI
Datapath
Backend
Access
DMA
Controller
Backend
and FIFO
Controller
Internal Data
Storage
128 Words
Backend Control
Data Handshake
Data
Figure 1-1 · CorePCIF Block Diagram
Target Controller
The Target controller implements the PCI Target function. It contains two sub-blocks: the PCI configuration space and
the address decoder logic. The configuration block implements a "type 0" PCI configuration space, supporting up to six
base address registers and the Expansion ROM register.
The actual registers implemented are described in Table 7-1 on page 105 .
The address decoder block monitors the PCI bus for address cycles and compares the address with the base address
registers configured in the configuration space. A match signals the datapath controller to start a PCI cycle.
Master Controller
The Master controller implements the PCI Master function. It contains three sub-blocks: the DMA registers, DMA
controller, and backend access logic. The DMA register block implements the four 32-bit registers that control the
DMA controller. These registers can be programmed either from the PCI bus or from the backend.
The DMA controller implements a PCI-compliant Master function that can burst up to 2 32 bytes of data without
intervention. The controller will stop a DMA burst automatically if the backend runs out of data, and restart when data
is available.
v4.0
15
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